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Altera_Forum
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8 years ago

1.8V HSTL Differential DDR output using ALTDDIO_OUT on Cyclone 10 LP

I need to drive multiple 1.8V HSTL differential pairs from a Cyclone 10 LP FPGA. The output is DDR, source synchronous. I am currently doing this with single-ended signals using the ALTDDIO_...
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Altera_Forum
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8 years ago

According to the device handbook, 1.8V differential HSTL standard is supported on all IO banks. No need to simulate anything, just assign a pin pair to the logical port.