Hi Guys, Can anyone help me i am nee to altera programming. Can anyone help me i am trying to write an up and down counter that counts from 0-15 with 2 bushbuttons and 2 7 segments display plaease help or guide me.

Here's a guide. 1. Use synchronous design techniques, eg., use the 50MHz clock on your board. 2. Design a synchronizer component, eg., dual DFF for converting an asynchronous external signal to a synchronous signal 3. Synchronize the external push button signals and then debounce them, i.e., check that the button transition from high to low or low to high is clean. You might need to use a counter to decide that button transitions are only recognized if the button state changes and is held for say 10 clocks. The button change can be converted to a single clock period wide pulse, and this can be the enable for your counter that drives the hex display. 4. Design a hex to 7-segment display driver 5. Wire it all together Don't go searching too far for source code, try and write it yourself, I'll show you examples if you cannot figure it out. Are you writing VHDL or SystemVerilog code? What board are you using? Cheers, Dave

I am writing a vhdl code and i cant figure it out

--- Quote Start --- I am writing a vhdl code and i cant figure it out --- Quote End --- Which step are you stuck on? Pick something simple. For example, start with the 7-segment decoder. That circuit can be combinatorial. The component input is 4-bits and the output is the 7-segment 7-bit value. Draw images of the digits 0 through F displayed on a 7-segment display and create a table of which bits need to be on or off. See if you can figure out how to implement that in VHDL. Don't worry if you cannot, just post the table (photo of paper is fine) to show you understand and tried. Cheers, Dave

7-segment diaplay 0-F ABCDEFG 0= 0000001 8= 0000000 1= 1001111 9= 0001100 2= 0010010 A= 0001000 3= 0000110 b= 1100000 4= 1001100 C= 0110001 5= 0100100 d= 1000010 6= 0100000 E= 0110000 7= 0001111 F= 0111000 a '0' means that the segment is on and a '1' means its off that is the table that i created thanks

Yep, you got it :) Now look at the VHDL implementation https://github.com/d-hawkins/hdl/blob/master/lib/hex_display/src/hex_display.vhd The std_logic_vector(6 downto 0) output is just (G,F,E,D,C,B,A), so the binary values in the table are in bit-reversed order to what you wrote above. That is just an implementation detail :) Cheers, Dave

0-15 counter | Altera Community

11 Replies

Altera_Forum
Honored Contributor
9 years ago
Here's a guide.

1. Use synchronous design techniques, eg., use the 50MHz clock on your board.
2. Design a synchronizer component, eg., dual DFF for converting an asynchronous external signal to a synchronous signal
3. Synchronize the external push button signals and then debounce them, i.e., check that the button transition from high to low or low to high is clean. You might need to use a counter to decide that button transitions are only recognized if the button state changes and is held for say 10 clocks. The button change can be converted to a single clock period wide pulse, and this can be the enable for your counter that drives the hex display.
4. Design a hex to 7-segment display driver
5. Wire it all together

Don't go searching too far for source code, try and write it yourself, I'll show you examples if you cannot figure it out.

Are you writing VHDL or SystemVerilog code?

What board are you using?

Cheers,
Dave

Forum Discussion

0-15 counter

11 Replies

Recent Discussions

Request for details

Agilex 5 RCOMP_GTS connection change and its effect on HVIO input pins

Leakage Current in MAX 10 Bank 1A (ADC Bank)

Missing AC characteristsics in A5E data sheet !

Refresh management (RFM) for LPDDR5 supported on Agilex 5?