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Altera_Forum
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16 years ago

Zentel A3S56D40ETP-G5 DDR-Ram Timing Problems

Hi, we have a Cyclone III Starter Kit. The DDR-Ram Chip is an Zentel A3S56D40ETP-G5. Refering to the specs of the chip, the timings are correct. No Preset is available in Quartus 9.1 (fully lic...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Can't you recompile the project with all the optimisations and reduced C library? Maybe it would fit then.

What do you mean by too old? If all the timing parameters are the same, it should work.