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Altera_Forum
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16 years ago

Zentel A3S56D40ETP-G5 DDR-Ram Timing Problems

Hi, we have a Cyclone III Starter Kit. The DDR-Ram Chip is an Zentel A3S56D40ETP-G5. Refering to the specs of the chip, the timings are correct. No Preset is available in Quartus 9.1 (fully lic...
Altera_Forum's avatar
Altera_Forum
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16 years ago

In the Nios IDE when you start a new project, you can select the "memtest" template. I haven't tried the new BSP tool, but I guess it's there too.

I believe the cycloneIII_3c25_start_niosII_standard given with the kit is using the DDR. Is it working on your new board?