writing/reading sram with cyclone3 in vhdl

You must think of the generated hardware. When you modify a signal in a clocked process, you in fact create a flip-flop that is able to hold a signal between clock edges. A flip flop needs a feedback of its output to function properly, and as a result in VHDL its output needs to be a signal that can be read back. Even if you don't explicitly read back a signal value, the generated hardware requires you to use a buffer.

As for your other question, I would have normally answered that you would need to do it in order for your code to be accepted by the synthesizer, but obviously in your case it works. I have no explanation for this, in my experience Quartus always rejected my code when I forgot to put a buffer. I wonder if they changed anything in the synthesizer to silently accept that construction (last time I made that kind of mistake was probably with Quartus 7.2).