Forum Discussion
Altera_Forum
Honored Contributor
15 years ago --- Quote Start --- In VHDL1993 you aren't allowed to read back the value of an 'out' port. --- Quote End --- - Yeah, i know, but i'm not trying to do it in my code or did i miss something? --- Quote Start --- This is a problem for registered outputs, because to maintain the value of a register between clock cycles, you need to be able to read it back. --- Quote End --- - Why do i want to do that? (except for the nWE signal for which i already did it)