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Altera_Forum
Honored Contributor
Honored Contributorwriting/reading sram with cyclone3 in vhdl
Hey, i'm trying to write and read to/from the sram with a cyclone3 fpga on a NEEK. I wrote a little code to check if it's working, but it doesn't and i tried very much around but to no avail. The ...
Altera_ForumHonored Contributor
Honored ContributorYou must remember that SignalTap does a sampling of all your signals with a clock. The signals are only sampled on the rising edge of that clock. If you used your SRAM_clk (or any other pll output at the same frequency) as the SignalTap sampling clock, then you will see SRAM_clk always at the same level.
Try to keep nOE at 0 for a longer time, it may need an extra cycle. If you still have problems, try to make a screenshot of the signaltap outputs and post it here.
