writing/reading sram with cyclone3 in vhdl

I didn't reply to your other question about buffers.

In VHDL1993 you aren't allowed to read back the value of an 'out' port. This is a problem for registered outputs, because to maintain the value of a register between clock cycles, you need to be able to read it back. That's why I thought that the synthesizer would reject your code. There are two usual ways to fix that:[list][*]declare the port as 'buffer' instead. 'buffer' is like 'out', but allows a read feedback for registers. The problem is that if that signal is connected to another output port on the higher level component, it needs to be declared 'buffer' too instead of 'out'. That's why I call 'buffer' a viral port type, that needs to be propagated along all the hierarchy. I usually advise against it.[*]use a signal as temporary buffer, like you did on the nWE signal. This unnecessarily complicates the code, but lets you keep the 'out' port type[/list]

This has been considered for a long time as one of the most stupid restrictions of VHDL. There has been a few changes to reduce this problem: in VHDL 2002, you can wire a 'buffer' port from a component to an 'out' port in an entity, removing the 'viral' constrain. In VHDL 2008, you can read back an 'out' port, removing the need for 'buffer'

Most people stick to VHDL 1993 though, for the sake of compatibility. According to Murphy's law, the day you switch to VHDL 2008, you'll need to use an old tool that only understands VHDL 1993 ;). I also have some customers that require VHDL 1993, so just to be sure I won't have to rewrite everything one day, I still stick to that old standard.