writing/reading sram with cyclone3 in vhdl

Sorry about that, I don't understand how I missed it... Better not to answer anything before my morning coffee ;)

You are right, you have the correct lines. But I still think you are missing output buffers for the other control signals, including nCS, nOE, nadsc. I thought the synthesizer wouldn't allow you to do that, especially if you are using VHDL 1993

For the SRAM, I thought that this kit used the same one than on the Cyclone III 3C120 development board (that I'm more familiar with, and that uses a 'false' SSRAM). I think you still have a 2 cycles latency to read data.

SignalTap isn't that difficult to learn, and it is a very very useful tool to debug any design. Spend a few hours now to learn to use it now, and you'll spare lots of hours of debugging later ;)