Forum Discussion
Altera_Forum
Honored Contributor
15 years agoThank you for your reply Daixiwen, but i think you didn't read everything.
First of all i'm talking about the SSRAM not the SDRAM, second as i already posted the clock frequency is 100Mhz and third, please have a look at the end of my code:nWE <= '0' when notWE = '0' else '1';
data <= memoryData when notWE = '0' else (others => 'Z'); Quartus II says i'm using VHDL 1993, should i change that? What do you mean by i am directly assigning values to some output ports? Are you talking about the control signals? And why shouldn't it work then? I will look up how to use SignalTAP, but i would be very grateful, if you'll have a look again and then maybe can help me :) Best regards, trigit