writing/reading sram with cyclone3 in vhdl

What is your clock frequency? The SDRAM is quite slow. Check for the datasheet but I think that the read latency is something like 80ns.

Second, you don't have any connection between your memoryData signal and your data vector. To handle the bidirectionnal bus, you should have something like this outside of the process:

data <= memoryData;

Then to write something on the bus, write it to memoryData, as you did. But to read, first you must set the bus in a tristate mode:

memoryData <= (others => 'Z');

and then read the data from data (not from memoryData!).

I haven't looked at everything, but it sooks like your notWE signal isn't connected to anything either. You are also directly assigning values to some output ports in the process, and I'm not sure it would work as expected. Are you using VHDL 2008? Because if you don't it should have generated an error.

Instead of using LEDs, you could use SignalTAP. It would let you see all the signals, and it is easier to check that everything works as expected.