Write from BRAM to 2D array in transpose manner

I have initialised single port BRAM of IP core with .coe file. BRAM is of 8x10 dimension having we_A,dout,din,addr,clk and declare a 2D array of 10x8 dimension.

I want to read from BRAM and write into the 2D array in transpose form, as the dimensions of both are different. I am using VHDL.

Below is the code. Kindly help me in transpose write in array. I am having problem in the logic inside the process.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;

use IEEE.NUMERIC_STD.ALL;

entity dummy_handle is
Port ( clk : in STD_LOGIC;
--test : out STD_LOGIC_VECTOR(7 DOWNTO 0);

rst : in STD_LOGIC);
end dummy_handle;

architecture Behavioral of dummy_handle is

type array2D is array (0 to 7 ) of STD_LOGIC_VECTOR (9 DOWNTO 0);
signal M: array2D;
signal addr_array : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";

signal we_A: STD_LOGIC_VECTOR(0 DOWNTO 0) := "0";
signal addr : STD_LOGIC_VECTOR(3 DOWNTO 0) := "0000";
signal din : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal test : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal dout : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal i : integer:= 0;

COMPONENT array_print
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;

begin
test <= dout;
print_array : array_print
PORT MAP (
clka => clk,
wea => we_A,
addra => addr,
dina => din,
douta => dout
);

dat_process: process(clk)

begin
if rising_edge(clk) then
if addr = "1010" then
addr <= "0000";
else
for addr_array in 0 to 7 loop
M(to_integer(unsigned(addr_array)),i) <= test(i);
addr_array <= addr_array + 1;
end loop;
addr <= addr + 1;
end if;
end if;
end process dat_process;
end Behavioral;