When LVDS using external PLL, how does Rx recover data and deal with phase changing?

Hi ,

Kindly find the explanation with using external PLL when using LVDS tx output

If you turn on the Use External PLL option for the Altera Soft LVDS transmitter, you require the following signals from the ALTPLL IP core: • Serial clock input to the tx_inclock port of the Altera Soft LVDS transmitter. • Parallel clock used to clock the transmitter FPGA fabric logic and connected to the tx_syncclock port

Reference page no: 21

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_lvds.pdf