Occasional Contributor
Frequent ContributorHi ,
Kindly find the explanation with using external PLL when using LVDS tx output
If you turn on the Use External PLL option for the Altera Soft LVDS transmitter, you require the following signals from the ALTPLL IP core: • Serial clock input to the tx_inclock port of the Altera Soft LVDS transmitter. • Parallel clock used to clock the transmitter FPGA fabric logic and connected to the tx_syncclock port
Reference page no: 21
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_lvds.pdf
Occasional Contributorwhat I mean is, on the other side of lvds, whose Rx receives this signal, how can it deal with the phase mismatch? Since Rx's clock is provided by its local PLL.
For example in the picture, board 1 send data with phase 1, and data is received by board 2. But board 2 has PLL clock with different phase 2.
How does Rx on board 2 sample this signal when phase are different?
