What would happen if VCCPD and VCCIO were delayed tens of minutes to power up after VCC was powered up already for 5CEA9 device?

In a 5CEA9 design， first power up VCC， and then VCCPD & VCCIO in all IO banks are not powered up right now, but at sometime later in tens of minutes，what will happen to the FPGA device? Will the FPGA...