What options are available for debugging and configuring the Stratix 10 MX FPGA development board, and how to do it?

Hie Han,

You can upload the configuration file (synthesized RTL that has been place and routed and assembled) either through PCIe or JTAG to the FPGA.

Hence yes, you can do it through the PCIe connection or using USB blaster cable that connects through JTAG.

Please refer to PG25 of the Stratix 10 MX development kit user guide on more information related to configuring the

FPGA.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-intel-s10-mx-devl-kit.pdf

Do let me know if you have additional questions.

Regards,

Nathan