What is the effect of nCE on passive serial configuration

Hi,

Thank you for your explanation. Apologize for providing you the wrong page number, it should be page#122 for passive. I do understand your question.

Below diagram is per Intel recommendation to program the device. Eventhough the nCE pin was grounded, the device were still program independently from each other.

FPGA#1 will be program first before FPGA#2. When FPGA#2 was programmed, FPGA#1 will be disabled. Hence it is recommended to follow Intel's handbook per the diagram and link provided to avoid failure as it has been successfully tested.

Other than Intel's recommendation, Intel will not be responsible for any failure.

To answer your question on what happens in the FPGA if you pulse nCONFIG low while nCE is high?

nCONFIG low: reset

nCE high: device disable

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51003.pdf (page122)

Hope this clarify. Thank you.

Regards,

Aiman