DZhu1New Contributor6 years agoWhat is the accuracy of dynamic delay chain(IO delay) and what is the adjustment range in Cyclone V FPGA Whether intel has some user guide about IO delay and introducing how to control the IO delay or not?Thanks
Recent DiscussionsAgilex™ 7 FPGA M-Series Development Kit_HBM2e Edition_REVB2_AlteraAgilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPsSyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series designR-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK_DEV_AGM039EA) does not workPCIe Root Complex on DK-A5E013BM16AEA