we need a list of rules , how to design the connections (address,data,clk) on the printed board , between the Cyclone V and the DDR3.

Have you checked the support documents and board design guidelines?

https://www.intel.com/content/www/us/en/programmable/products/fpga/cyclone-series/cyclone-v/support.html

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/board-design-guidelines.html

Also, you can use the documentation from one of the dev kits as a starting point/guide:

https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-gx.html

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