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SERMASWATHIKA's avatar
SERMASWATHIKA
Icon for Contributor rankContributor
2 years ago

warnings on fitter for design

Hi Team, I have compiled the design with ddr3,nios ii processor, avalon mm and other ip interfaces. I have used the ddr3 memory with 400 mhz and other interface uses afi_half_clk like that I ...
Fpga Devkit
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi SERMASWATHIKA,


I'm sorry for the delay to respond in this forum.


From my observation, the warning messages are telling about the clock port is not used so it's connected to GND.

If you already assigning all pins, then it's should be okay.

Unless there are some floating pins in your design, the Quartus will identify it as unused pin then connected to GND.


There should be some IPs in your design, can you identify which IP that causing this warning by removing the IP?

This should be able to isolate this issue.


Thanks & Regards,

Adzim