New Contributor
Super ContributorHello,
Welcome to INTEL forum. VID is basically will be different from board to board depends on the on-board power regulator design.
For your case, the easier way is to refer to S10 GX dev kit reference design, and check out the VID setting in reference design Quartus design and *.qsf file
https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s10-fpga.html
New ContributorThanks, but there is only one qsf in the software package for the GX dev kit (s10_fpga_golden_top.qsf) and it does not have those settings in it. I started with that qsf for my own design and still got these errors.
