Verilog Code for Setting up Clock on FPGA with Differential Clocks

You can use the differential clock in exactly the same way as a single ended clock - i.e. having an input wire in your top level (e.g. called `clock` or whatever name you wish). You only need an input wire for the positive (_p) pin of the differential pair.

In the pin planner (or assignement editor), assign this input to the pin that your differential clock connects to, specifically the "_p" pin of the differential pair, and select an appropriate differential IO standard and termination (e.g. on the Agilex, "True Differential Signaling" if that is correct for the signal on your board).

Quartus will automatically insert a differential IO buffer for you and connect it to both the _p pin you explicitly specified and the corresponding _n input pin of the differential pair which it will infer.