Forum Discussion
Altera_Forum
Honored Contributor
17 years agoHi,
If you are talking about transceivers then they must have bit rate restrictions due to CDR circuitry(PLL can only accept a range of input clock frequency). You can prove that by instantiating an LVDS and entering your rates then check the input clock frequency to PLL. If you are talking about using the lvds pins only then they should accept any data rate up to an allowed maximum. I certainly don't need transceivers for 100 Mbps Kaz