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Altera_Forum
Honored Contributor
14 years agoHi Leen,
It is a silly mistake from side.I had forgotten to put clock output of pll(clk of ssram) in the port section of entity of top level vhdl code.Hence had not assigned the pin for ssram clock. now,the problem is solved.I am able to write into & read from SSRAM. Regards, Raghavendra.S