Using On Chip Memory (tightly coupled memory) in Nios 2

Add on-chip memory as dual port. Make sure to clock each port separately Connect one port to your NIOS system. The other port will be used by your VHDL code.

If your VHDL is independent of QSYS, export the other port of the on-chip memory, and re-generate the QSYS module. The QSYS declaration will now have the signals needed by the other port of on-chip memory.

If your VHDL is implemented as a QSYS component, edit the definition to include an Avalon master port. Connect this port to the other port of the on-chip memory.

In either case your VHDL code will need to follow the specifications to implement the Avalon master port to talk to the memory. Search for "Altera Avalon spec" for more information. It's similar to interfacing to wishbone or AXI.