New Contributor
Frequent Contributor Hi DP7,
For Cyclone V, the maximum speed you can achieve on interface is 400 MHz. The fabric interface supports frequencies in the range of 10 MHz to one-half of the memory interface frequency. For example, for an interface running at 400 MHz, the maximum user logic frequency is 200 MHz. So, it is impossible to sample ADC at 500MHz as the maximum it can go is up to 200 Mhz and I am really sorry for the inconvenience caused. This information covered in EMIF estimator.
The memory controller access using Avalon Memory-Mapped (AVMM) Interface as long as the logic/master component comply with the AVMM specification. For the timing diagram and AVMM specification, you can refer to Avalon Interface specifications. For Avalon Memory-Mapped Interface, you can refer to this chapter.
You can see on this chapter, it explain the details of each avalon mm signals and there is timing diagram for clearer understanding.
Hope this helps.
