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Altera_Forum
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13 years ago

Using CML or DQS transceiver pins as LVDS possible in Stratix V DSP Dev Kit?

Hi, Forgive me if the question is basic. I am new to the field of FPGAs. I give a short version of the question. And a long version of the question. For those interested :). Note: Re...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Hi,

Thanks for the informative reply.

I understand your reference regarding SERDES requiring frame clocks for synchronization and the PLL.

But what if the frame clock is embedded in the signal itself using a unique pattern.

And the data is encoded for DC balancing..

If I AC couple the LVDS transmitters from the DE3 board to CML Receivers of the Stratix V board, embed a clock signal in the data stream and encode the data for DC balancing, I should be able to transfer the data right?

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Zubair