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Altera_Forum
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15 years ago

USB Sample in Cyclone II starter Kit

Hi I am trying to use the CII_Starter_USB_API_v1 demonstration supplied with the Cyclone II FPGA starter kit. This lets you send a file to flash or SDRam, and read back a file from Flash o...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Thank you for your reply.

1- Regarding the input clock frequency “fHSCLK”, from the previous mentioned tables, the lowest value of its maximum is 155.5MHZ. So, the lowest value of the maximum fHSCLK for the device (EP2C20Q240C8N) is 155.5 MHZ. Kindly confirm.

Kindly confirm if it is applicable to use the device (EP2C20Q240C8N) in my design with 125 MHZ taking into consideration that, 150 MHZ will be generated internal the FPGA from the used 125 MHZ).

Reference to “Cyclone II Device Family Data Sheet” page 2–53,which stated that: the Cyclone II devices can transmit and receive data through LVDS signals at a data rate of up to 640 Mbps and 805 Mbps. Can I implement the 1G Ethernet using the “EP2C20Q240C8N” ?