Understanding SW3 settings in Agilex Devkit

Hi anrfpga

There are 2 modes for each SW3 settings is because there are 2 options to connect the JTAG connection.

One way is through an external Intel FPGA Download Cable II dongle connected to the JTAG Header connecter or through an internal Intel FPGA Download Cable II dongle connected through using a usb cable.

Refer to Section A.2.1 and A.2.2.

To be in Mode 1 refers to when you connect using the internal Intel FPGA Download Cable II dongle and Mode 3 refers to when you connect using an external Intel FPGA Download Cable II dongle.

"Chained HPS with SDM nodes externally" in Mode 001 means that it will connected together through the external Intel FPGA Download Cable II dongle. You could see it in the JTAG chain.

Regards

Jingyang, Teh

Hi Jingyang,

Thanks for your reply. That makes sense. Can you point me to A.2.1 and A.2.2? I could not find these sections in the document I am referring to.

When I change switch to Mode 001, I am getting "Unable to scan device chain. Can't scan JTAG chain" error instead of seeing the HPS in the JTAG chain. My SW1 settings are set to JTAG configuration mode and SW3 settings are set to (OFF/ON/ON/ON/ON/OFF/ON/ON = SW3.1 and SW3.6 are set to OFF). How could be the issue here?

Running the JTAG chain integrity test in the JTAG chain debugger is throwing

Error: JTAG chain problem detected.

Error: No device detected. Detected 1's at TDI pin.

Hi anrfpga

Sorry that I pointed you to the wrong section.

There is a statement in the document that you are viewing just before Table 9 .

"Intel® Agilex™ HPS JTAG slave can be accessed from either SDM dedicated JTAG pins or HPS dedicated I/Os."

With the current switch settings, are you able to detect any device on the chain with the "AutoDetect" button?

Do you encounter any JTag error if you follow the default settings?

Regards

Jingyang, Teh

Hi Jingyang,

No, clicking Auto Detect is throwing the error that I mentioned. However, disabling the HPS (setting SW3.1 to ON) from the JTAG chain is resolving the broken chain issue but that defeats the purpose of having HPS external to the SDM.

Rest of the modes are all working fine and I am able to program the FPGA.

Thanks

Nikhil

Hi Nikhil

Are you using the internal or external usb blaster currently?

If you are using an external usb blaster, is it connected to the J19 port?

Regards

Jingyang, Teh

Hi Jingyang,

I am using the internal usb blaster connected to the CN1 port.

Regards

Nikhil

Hi Nikhil

Are you using the GHRD FPGA configuration currently or using a custom FPGA configuration?

The term "Chained HPS with SDM nodes externally" refers to the HPS is chained to the SDM through the Intel MAX10.

"Chained HPS with SDM nodes internally" refers to the HPS is chained to the SDM through the dedicated JTAG pins.

Regards

Jingyang, Teh

Hi anrfpga

Any update on this case?

Regards

Jingyang, Teh

Hi Jingyang,

I am using the GHRD FPGA configuration. But, I am not sure how that impacts the JTAG chain.

Based on your reply, I tried more configurations. The first one with ON/OFF/ON/ON/ON/OFF/ON/ON (SW3.2 and SW3.6 are OFF = MAX10 FPGA enabled) was working fine and had the AGFB014 and MAX10 in the JTAG chain and the second one with OFF/OFF/ON/ON/ON/OFF/ON/ON (SW3.1, SW3.2 and SW3.6 are OFF = Both HPS and MAX10 enabled) had a broken chain issue. I have attached the JTAG debugger error.

So, with internal USB blaster cable, is the second configuration invalid?