Forum Discussion
Occasional ContributorUnderstanding address map in EMIF
For the address ordering that you used:
CS-CID-Row-Bank-Column-BG
The CS is available only when there is multiple rank.
The CID is for 3D stacked interface. No CID bit in this configuration.
Row address width = 15.
Column address width = 10.***
Bank address width = 2.
Bank group width = 2.
***(Lower 3 bits has been set to 0 because Avalon bus is 8x wider than EMIF bus in Quarter rate. Therefore it's removed when mapping to Avalon address)
The ordering will be as below:
Row[14..0] = amm_address[25..11]
Bank[1..0] = amm_address[10..9]
Column[9..3] = amm_address[8..2]
BG[1..0] = amm_address[1..0]
Regular ContributorFor the address ordering that you used:
CS-CID-Row-Bank-Column-BG
The CS is available only when there is multiple rank.
The CID is for 3D stacked interface. No CID bit in this configuration.
Row address width = 15.
Column address width = 10.***
Bank address width = 2.
Bank group width = 2.
***(Lower 3 bits has been set to 0 because Avalon bus is 8x wider than EMIF bus in Quarter rate. Therefore it's removed when mapping to Avalon address)
The ordering will be as below:
Row[14..0] = amm_address[25..11]
Bank[1..0] = amm_address[10..9]
Column[9..3] = amm_address[8..2]
BG[1..0] = amm_address[1..0]
Occasional ContributorOh, I see. I did not know this fact. Thank you so much for your explanation.
- Mahdi
