Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

TTK .. having difficulties

http://www.alterawiki.com/wiki/use_transceiver_toolkit_to_measure_pci-express_link_signal_integrity Using this reference design ... I tried with Quartus 13.1 and 14.0 and in both cases after lo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Wow, some eye .... I wish I could get that ... the thing is the example I have is an Altera example ... and it should all be connected correctly if it is an example ... I get nothing on the TKK window ... the first one you have ... One thing is I have Quartus 13.1 on one PC and 14.0 on the other .. only the one with 14.0 gets the TTK to open ... possible I need if check if that is included in the Quartus download.... The note seemed to imply that with 13.1 s .sv file would need to be replaced and the design re-synthesized and .sof reloaded ... was that the case for you ...

On an unrelated subject ... I have “Gen3 x8 Avalon-ST 256-bit - Stratix V” design and it has excellent Inbound Gen3 x8 performance ... I want to add a BAR and On Chip Memory behind it to test Outbound preformance for Gen3 x8 ... I am not sure how to do that . Any ideas ... the HIP component says I can add BAR's but they don't appear as a Avalon MM master port on the component GUI is QSYS.

Thanks, Bob.