I'm having trouble to bring up the TSE MAC to Ethernet interface on the Stratix II GX PCIe board. I was able to instantiate a triple speed Ethernet MAC and build logic around it. The loopback at the GMII interface seems work fine. However, I'm not able to send any packet out via the on board Marvell 88E1111 Ethernet transceiver. I suspect I need to program the registers in it via the MDIO. Is there a register map or data sheet of the 88E1111? Or is there anything else I'm missing? Thanks.

Hey guy, I have successfully make it works before(same dev board, same on-board PHY). A few tricks: 1. You need to do a RESET on the onboard Marvel PHY when you power up the board (only for this particular onboard PHY, I have no such problem with other Marvel88E111 daughter card or SFP). It is described in the Marvel document as about 10ns second reset (if not mistaken). You can either tie the PHY reset pin to the on board reset button or just use some hard logic to do it. Very odd, powerdown/powerup the board doesn't cleanly reset the PHY. (2. to 4. only apply if you are not using the sample application/example design/default TSE driver) 2. You need to make sure that your MAC, ethermode/speed bit in the command config register represent the mode the PHY is currently working at 3. Remember to turn off the INTERNAL_LOOPBACK register bits:) 4. Make sure that you know you are using/not using the 16-bits byte shifting/alignment feature (synthesis/register option in TX/RX_CMD_STAT), I don't think you need a Marvel Datasheet, all the general settings of any PHY is described in the TSE documentation, unless you need some extended/proprietary settings like turn on the automatic clock adjustment for RGMII interface.

Thanks. I somehow got it to work after playing with it for a while. I added some "redundant" initialization sequence in the logic including a reset of the PHY after power up. I suspect that's what made it work as you pointed out. --- Quote Start --- Hey guy, I have successfully make it works before(same dev board, same on-board PHY). A few tricks: 1. You need to do a RESET on the onboard Marvel PHY when you power up the board (only for this particular onboard PHY, I have no such problem with other Marvel88E111 daughter card or SFP). It is described in the Marvel document as about 10ns second reset (if not mistaken). You can either tie the PHY reset pin to the on board reset button or just use some hard logic to do it. Very odd, powerdown/powerup the board doesn't cleanly reset the PHY. (2. to 4. only apply if you are not using the sample application/example design/default TSE driver) 2. You need to make sure that your MAC, ethermode/speed bit in the command config register represent the mode the PHY is currently working at 3. Remember to turn off the INTERNAL_LOOPBACK register bits:) 4. Make sure that you know you are using/not using the 16-bits byte shifting/alignment feature (synthesis/register option in TX/RX_CMD_STAT), I don't think you need a Marvel Datasheet, all the general settings of any PHY is described in the TSE documentation, unless you need some extended/proprietary settings like turn on the automatic clock adjustment for RGMII interface. --- Quote End ---

Hi, I've got a pci express demo board and i want to use GbEthernet communication. For now, I was able to instantiate TSE MAC and make logic for initialization. with a big sate machine just like in the provided altera test bench. That seem's to work. But when i send frame on tx fifo interface, nothing come back on the rx fifo interface. And loopback is activate... I think some initializations are missing. I put below my init sequence. could you help me and say me if I wrong or not ? Init TSE MAC Sequence: - Read Version (@0x00) and check 0x00000800 - Write Scratch (@0x01) to 0xAAAAAAAA, readback and check - Write Config (@0x02) to 0x040083EB TX_ENA & RX_ENA = 1 ETH_SPEED = 1 PAD_EN = 1 CRC_FWD & PAUSE_FWD = 1 PAUSE_IGNORE = 1 TX_ADDR_INS = 1 LOOP_ENA = 1 RX_ERR_DISC = 1 - Write mac_0 & mac_1 (@0x03 & 0x04) to 0x22334450 & 0x0000EE11 (choose MAC: EE1122334450) - Write ipg length (@0x17) to 0x0C - Write frame length (@0x05) to 1518 (0x5EE) - Write pause quanta (@0x06) to 0x0F - Write rx_section_empty (@0x07) to 0x00 - Write rx_section_full, tx_section_empty, tx_section_empty (@0x08, 0x09, 0x0A) to 0x10 - Write rx_almost_empty, rx_almost_full, tx_almost_empty (@0x0B, 0x0C, 0x0D) to 0x08 - Write tx_almost_full (@0x0E) to 0x0A - Finally, Write mdio_addr0 (@0x0F) to 0x12. (Sorry for all this details but I wan't you have all the informations to help me!) Did I forget something during init process ? Could you help me ? Thanks you very much! Fabrice.

--- Quote Start --- Hey guy, I have successfully make it works before(same dev board, same on-board PHY). A few tricks: 1. You need to do a RESET on the onboard Marvel PHY when you power up the board (only for this particular onboard PHY, I have no such problem with other Marvel88E111 daughter card or SFP). It is described in the Marvel document as about 10ns second reset (if not mistaken). You can either tie the PHY reset pin to the on board reset button or just use some hard logic to do it. Very odd, powerdown/powerup the board doesn't cleanly reset the PHY. (2. to 4. only apply if you are not using the sample application/example design/default TSE driver) 2. You need to make sure that your MAC, ethermode/speed bit in the command config register represent the mode the PHY is currently working at 3. Remember to turn off the INTERNAL_LOOPBACK register bits:) 4. Make sure that you know you are using/not using the 16-bits byte shifting/alignment feature (synthesis/register option in TX/RX_CMD_STAT), I don't think you need a Marvel Datasheet, all the general settings of any PHY is described in the TSE documentation, unless you need some extended/proprietary settings like turn on the automatic clock adjustment for RGMII interface. --- Quote End --- Hi, I am using Stratix II gx board and TSE MAC core. Can u please give some more details (logic )on reset logic required to use MARVELL PHY. Thanks

Marvel Data sheet ? Where did you find that, I have been googling around all over and all I find is the 2 page Product brief. Any help greatly appreciated! -Art

TSE MAC and Marvell 88E1111 | Altera Community

42 Replies

Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
the MDIO is a shared bus. You can have a signgle MDC and a single MDIO pin on the FPGA, connected to both MDC and MDIO pins on the PHY chips.
If they are already connected separately, then you'll have to write a little logic to merge them into a single bus inside the FPGA. The MDC is output only so you can just duplicate the signal. The MDIO is bidirectionnal though, so you need a bit more. When used as an output you can duplicate it to both PHYs too, and when used as an input, just do an AND between the two inputs from the PHYs before feeding it to the TSE.
--- Quote End ---

Hi,

Thank you very much for your prompt & valuable reply.

We would like to confirm the connection between the TSE MAC & the 2 PHYs, so kindly check the attached image.

I thought that we may need OR not AND between the inputs from the two PHYs, so kindly explain.

Best Regards.
Altera_Forum
Honored Contributor
14 years ago
Yes this should work. The MDIO pin is supposed to have an external pull-up, and is an open drain output on each PHY. As only one PHY willl use it at a time, you can use an AND gate to transmit a 0 to the TSE core when one of the PHY drives a 0 on their MDIO pin.

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TSE MAC and Marvell 88E1111

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