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Honored Contributor
Honored ContributorTSE connection problem
Hi all, I got a problem when I tried to connect the TSE MAC to the PHY, some thread said that the enet_gtx_clk should be connected to a 25MHz clock along with the tx_clk_to_the_tse_mac, but my...
Altera_ForumHonored Contributor
Honored ContributorAnother problem is that there are many assignment like this:
assign fsa = address_to_the_cfi_flash_64m[25:1] the fsa[24..0] and address_to_the_cfi_flash_64m[25:1] are both output, how can I connect them? And in bdf should i write a new block which made fsa become [25..0] to make it connected?
