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Ratan's avatar
Ratan
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2 years ago
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Trying to configure my de1-soc board with oneAPI

I am trying to run the sample program vector-add which was obtained from the oneapi-cli menu and I am just not sure if the de1-soc board is an officially supported board for the oneapi base toolkit. Well, I assumed that I had to follow the development kit first and then move onto the deployment kit which includes quartus prime and the BSP(along with the development flow) that needs to be used to deploy a custom logic onto an FPGA.

Can anyone tell me if im moving in the right direction? and whether if I have to do the jupyterlab intro along with the FPGA emulation to actually understand how to get the de1-soc and oneapi to work together ?

  • Hi @Ratan,


    You should changed all the includes statement based on what is being mention previously to fixed the fatal error mention.

    Apologies as I am confused, are you saying you have reverted back to the old include statement and issues is fixed?

    Unsure of what stage you are in now, please do share the project that you are facing issues with, so that we can better understand the current stages you are at.

    Hope to hear from you soon.


    Best Wishes

    BB


18 Replies

  • Hi @Ratan,


    I see, after going through the post mention in the other thread it seems that you are still having a compilation issues on the code, where compiler are complaining 'fatal error that says: CL/sycl/INTEL/fpga_extensions.hpp . file not found'.


    It seems that the changes are not taking effect as compiler are still getting the previous path and throwing error. (i.e., instead of '#include <sycl/ext/intel/fpga_extensions.hpp>)

    Please do ensure that correct .cpp or check all other .cpp files to ensure changes are made.

    Hope that clarify.


    Note: please do reply to this thread for me to better observe the issues you have.


    Best Wishes

    BB


  • Ratan's avatar
    Ratan
    Icon for New Contributor rankNew Contributor

    I just reverted back to the old configuration of including #include <CL/sycl/INTEL/fpga_extensions.hpp> , i also have it saved in the testdir directory but I have no errors like before. no fatal error display. It just runs through all the cells but has no 'VERIFICATION PASSED' output... I dont know if i should skip the hough transform emulation for now? it seems to behave weirdly and a trial and error process didnt exactly work and I am not quite sure how to check all other .cpp files?

    any advice on this?

    Followed the video again to check if i missed any steps but there is nothing that I missed. The process has alternating behavior.

  • Hi @Ratan,


    You should changed all the includes statement based on what is being mention previously to fixed the fatal error mention.

    Apologies as I am confused, are you saying you have reverted back to the old include statement and issues is fixed?

    Unsure of what stage you are in now, please do share the project that you are facing issues with, so that we can better understand the current stages you are at.

    Hope to hear from you soon.


    Best Wishes

    BB


  • Ratan's avatar
    Ratan
    Icon for New Contributor rankNew Contributor

    I am at the same stage, which is;

    I was performing emulation of hough transform for FPGA's on Jupyterlab but then all i had to do was run the cells:


    I get the following error ->

    ## u196294 is performing Hough Transform compilation emulation notebook.
    icpx: warning: use of 'dpcpp' is deprecated and will be removed in a future release. Use 'icpx -fsycl' [-Wdeprecated]
    src/original/hough_transform.cpp:8:10: fatal error: 'CL/sycl/INTEL/fpga_extensions.hpp' file not found
    #include <CL/sycl/INTEL/fpga_extensions.hpp> //try this and prev
    ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    1 error generated.
    /bin/bash: bin/hough_transform.emu: No such file or directory

    I am not sure how to solve this. I am unable to find the header files that they are supposed to include. I cant even find the parent directory which is supposed to be 'CL'.

    Has anyone done fpga emulation using jupyterLabs and gone through the same problem?
    i am eagerly looking for help, thanks.

    I have been stuck on this for more than a week now but I had to inform you that the conversation that you linked me to, I tried that even included the ! mkdir bin statement which was used to solve the other users problem. unfortunately that did not solve mine, since i already had a directory named bin within the testdir directory.

    can you do a new tutorial of the fpga emulation and cell running process to get the expected output - 'VERIFICATION PASSED'

    I dont know which path to check and how to overcome this issue.

    Thank you for all your help till now as well, I really appreciate it.

  • Hi @Ratan,

    Noted on the stage that you are still stucked.

    I have pulled the similar hough example mention, and have made the necessary changes line #9, #72 and #76.

    Attached are the zip files that contain hough_transform.cpp that I have changed from my end which is successfully compiled and run emulation.

    Would suggest perhaps to compare with your .cpp files to see if any differences.

    Once .cpp files are made, please go ahead to create a bin directory as below:

    With that you would be able to run the emulation and get the following result as below:

    Note: you can ignore the warning for now as the example code might have some outdated code.

    Best Wishes

    BB

  • Hi @Ratan,


    Greetings, as we do not receive any further clarification/updates on the matter, hence would assume challenge are overcome. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. For new queries, please feel free to open a new thread and we will be right with you. Pleasure having you here.


    Best Wishes

    BB


    p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.