ContributionsMost RecentMost LikesSolutionsRe: can oneapi run on all FPGA boards? Yeah sure, can you shoot me an email and I will contact you from that point on wards and we can arrange a time ? Thank you so much for your help! Re: can oneapi run on all FPGA boards? I don't understand what you mean by 'build on oneAPI'. Let's say my goal is to work with the Hough Transform prj folder which is on jupyter labs, would I have to make a copy of that file on my linux system and then use oneAPI to generate an rtl file which can then be used on quartus prime to deploy it on my de1-soc board ?? Re: can oneapi run on all FPGA boards? Hello, any updates on this important topic? Re: can oneapi run on all FPGA boards? I might have not explained the whole case clearly,sorry. So here are my questions , in a simplified manner: .I was making use of oneapi to deploy the development flow(using quartus prime lite + bsp) onto my de1-soc. . I was not planning to download the bsp for the de1-soc from an intel source since it is not supported and the bsp simply isnt present for downaload. .My idea was to use oneapi to generate an RTL file of the hough transform(sycl - on jupyterLabs) and then use that rtl file to generate a custom bsp from quartus prime lite. . If I am not able to generate an RTL file off oneapi for a provided SYCL script, could I do it for a sample program like vectoradd which is provided from the oneapi-cli menu? or is it not possible to do so at all? Is my plan to use the development flow by generating a custom bsp from quartus prime after generating an RTL file from oneapi not valid at all? . I would then proceed to deploy the bitstream onto my de1-soc after the above steps. Please let me know if my plan to integrate this particular flow is reasonable. If it is, can I please know how to start off with this process? I really have no idea how to start off to convert the SYCL code into a rtl file using oneapi. Although I am familiar with deploying logic onto the de1-soc after retrieving the .sof file( I have experience working with quartus prime and qsys to deploy logic onto my de1-soc) but my project now ,is to develop and deploy projects onto boards using oneapi instead of qsys and quartus. Re: can oneapi run on all FPGA boards? Hello, any updates on this topic? Re: can oneapi run on all FPGA boards? Also will quartus prime lite edition let me proceed with this plan? or does it have to be the standard or pro edition ? can oneapi run on all FPGA boards? I currently have a de1-soc but I was unsure if i can use the oneapi base toolkit + Quartus prime + bsp on it to deploy custom logic? Also do you think it would be possible for me to deploy the hough transform on my de1-soc by using the fpga-selector ? I I just completed the steps for emulation,optimization and bit stream generation on jupyterlab to get familiar with the development/deployment flow and my next step was to integrate oneapi with a board. What do you suggest I do as my next step? I have also completed some projects previously using quartus prime, qsys and my de1-soc board. My goal was to try and run these same projects on the same de1-soc or an approved board(as given on the website) but with oneapi this time and code the same script in CPP or DPCPP. Thank you. Re: Trying to configure my de1-soc board with oneAPI I am at the same stage, which is; I was performing emulation of hough transform for FPGA's on Jupyterlab but then all i had to do was run the cells: I get the following error -> ## u196294 is performing Hough Transform compilation emulation notebook. icpx: warning: use of 'dpcpp' is deprecated and will be removed in a future release. Use 'icpx -fsycl' [-Wdeprecated] src/original/hough_transform.cpp:8:10: fatal error: 'CL/sycl/INTEL/fpga_extensions.hpp' file not found #include <CL/sycl/INTEL/fpga_extensions.hpp> //try this and prev ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1 error generated. /bin/bash: bin/hough_transform.emu: No such file or directory I am not sure how to solve this. I am unable to find the header files that they are supposed to include. I cant even find the parent directory which is supposed to be 'CL'. Has anyone done fpga emulation using jupyterLabs and gone through the same problem? i am eagerly looking for help, thanks. I have been stuck on this for more than a week now but I had to inform you that the conversation that you linked me to, I tried that even included the ! mkdir bin statement which was used to solve the other users problem. unfortunately that did not solve mine, since i already had a directory named bin within the testdir directory. can you do a new tutorial of the fpga emulation and cell running process to get the expected output - 'VERIFICATION PASSED' I dont know which path to check and how to overcome this issue. Thank you for all your help till now as well, I really appreciate it. Re: Trying to configure my de1-soc board with oneAPI I just reverted back to the old configuration of including #include <CL/sycl/INTEL/fpga_extensions.hpp> , i also have it saved in the testdir directory but I have no errors like before. no fatal error display. It just runs through all the cells but has no 'VERIFICATION PASSED' output... I dont know if i should skip the hough transform emulation for now? it seems to behave weirdly and a trial and error process didnt exactly work and I am not quite sure how to check all other .cpp files? any advice on this? Followed the video again to check if i missed any steps but there is nothing that I missed. The process has alternating behavior. Re: Trying to configure my de1-soc board with oneAPI Yeah I asked all the following questions on the link you provided me. It was a resolved case but I decided to ask my questions on there because you can have better references. Please do check as I am eagerly waiting for your response. Thank you so much.