Trouble with Arria10 dev kit FPGA EMIF

I am on a similar path as you. I am using the A10 SoC Devkit trying to get a handle on DDR4 use. i am using Quartus v17.0.2 and when I create the example design it runs fine and I can see sucessful reports in the EMIF toolkit, but in my program using the same DDR4 QSYS file I get no memory function. I am getting good timing closure (using the reference recommendations), but if I use SignalTap I can see that the emif_ready line never changes when I write or read (and of course my read result is always zeros).