Hi.. Need help here!! I've been struggling for a couple weeks. I have a stratix III board with a on-board Marvell PHY. I just tried to make a triple speed ethernet working on MII mode (10/100 is good enough, i don't need high speed.) So i just take CycloneIII's example (from its development kit) as a reference for the SOPC and follow the manual of TSE. Also I add a redundunt reset circuitry for this enet_reset since there is a certain issue on this kind of setup which i got from this forum. However, it never worked. Symton is as follows.. BTW i use Simple socket server on NIOSII and Quartus8.0 SOPC. PHY can receiver packet (it seemed.. because i can see RX LED is blinking when i tried 'ping').. but no Tx ( i never see TX LED blinking.) Also i set a break point on SGDMA rx int.. it never asserted. So i guessed TSE_MAC never receives data from PHY. I know there should be some tools which could verify something for me.. Sorry.. I'm a newbid in Altera FPGA. So if you think there is anything i should check or modify.. Please let me know. Of course, if you make it work before, could you please share that with me? Thanks.

First you need to check that the PHY didn't auto-negotiate a 1Gbs link. Because in that case if you try to use the MII interface it won't work. Then you can add some Signal Tap probes to see what signals are coming from the PHY it should help you understand why the MAC doesn't process them.

Thanks for the reply. I was connecting the ethernet cable into 10/100 router and i gounded set_1000 to make sure it's not running on Gigabit. Also i checked the LED indicator with the right ethernet mode indication. For the Signal Tap, I will try it right away. BTW, i happened to see some threads mentioning about timing constraints on TSE_MAC related signals. Do you think that's very likely apply in my case. I believe I didn't touch that at all..:(

You definitively need to constrain the I/O signals on the MII bus. It could explain your problem.

Hi.. Help!! I've tried to do the time constaints on all tse_mac related signals (following tse_mac_constraints.sdc) and i can get the report of the time request without any negative slack in all models. However, after i loaded the image on the board, it's still about the same thing. In 10/100 mode (GMII/MII), only RX LED is on, and never see TX LED lit. I also tried RGMII mode, and followed the timing scripts you mentioned in the other thread. Fortunetely, i can see both RX and TX LED lit. However, the data still can't get through.. (but i think its situation is better than MII mode) So my question is do i have to follow that sample timing scripts which you provide (like chaning 125MHz to 25MHz for Ethernet 100 mode)? Or i miss something here? (maybe i should have Marvell PHy spec and follow its recommendaton for the time constraints) BTW, the timing script:# **************************************************************# Create Clock#**************************************************************create_clock -name {clkin_125} -period 8 [get_ports {clkin_125}]create_clock -name {enet_rx_clk} -period 8 [get_ports {enet_rx_clk}]#**************************************************************# Create Generated Clock#**************************************************************derive_pll_clocksset enet_tx_in_clk gbe_pll:inst12|altpll:altpll_component|gbe_pll_altpll:auto_generated|wire_pll1_clk[0]set enet_tx_out_clk gbe_pll:inst12|altpll:altpll_component|gbe_pll_altpll:auto_generated|wire_pll1_clk[1]#**************************************************************# Set Input Delay#**************************************************************set_input_delay -clock enet_rx_clk -min 1.5 [get_ports {enet_rxd [*] enet_rx_dv}] -add_delayset_input_delay -clock enet_rx_clk -max 2.5 [get_ports {enet_rxd [*] enet_rx_dv}] -add_delayset_input_delay -clock enet_rx_clk -clock_fall -min 1.5 [get_ports {enet_rxd [*] enet_rx_dv}] -add_delayset_input_delay -clock enet_rx_clk -clock_fall -max 2.5 [get_ports {enet_rxd [*] enet_rx_dv}] -add_delay#**************************************************************# Set Output Delay#**************************************************************set_output_delay -clock $enet_tx_out_clk -max 1 [get_ports {enet_txd [*] enet_tx_en}]set_output_delay -clock $enet_tx_out_clk -min -1 [get_ports {enet_txd [*] enet_tx_en}] -add_delayset_output_delay -clock $enet_tx_out_clk -clock_fall -max 1 [get_ports {enet_txd [*] enet_tx_en}] -add_delayset_output_delay -clock $enet_tx_out_clk -clock_fall -min -1 [get_ports {enet_txd [*] enet_tx_en}] -add_delay#**************************************************************# Set Clock Groups#**************************************************************set_clock_groups -exclusive -group [get_clocks {clkin_125 enet_tx_in_clk enet_tx_out_clk}] set_clock_groups -exclusive -group [get_clocks {enet_rx_clk}]# **************************************************************# Set False Path#**************************************************************set_false_path -from [get_ports {enet_mdio}]set_false_path -to [get_ports {enet_mdc enet_mdio}]set_false_path -setup -rise_from $enet_tx_in_clk -fall_to $enet_tx_out_clkset_false_path -setup -fall_from $enet_tx_in_clk -rise_to $enet_tx_out_clkset_false_path -hold -rise_from $enet_tx_in_clk -rise_to $enet_tx_out_clkset_false_path -hold -fall_from $enet_tx_in_clk -fall_to $enet_tx_out_clk#**************************************************************# Set Multicycle Path#**************************************************************set_multicycle_path -from $enet_tx_in_clk -to $enet_tx_out_clk -setup -start 2#**************************************************************# Set Maximum Delay#**************************************************************set_max_delay -from $enet_tx_out_clk -to [get_ports {enet_gtx_clk}] 20#**************************************************************# Set Minimum Delay#**************************************************************set_min_delay -from $enet_tx_out_clk -to [get_ports {enet_gtx_clk}] 0

IIRC the Altera TSE mac doesn't work very well with RGMII at 10/100 speeds, so you should stick to MII. The constraints will need some adjustments as you are not in DDR anymore. Did you try to connect SignalTap probes to the MII signals to check if anything is received on that side?

Triple speed ethernet and Marvell Phy on Stratix III

29 Replies

Altera_Forum
Honored Contributor
17 years ago
Alright.. here you go!!# **************************************************************# Create Clock# **************************************************************
create_clock -period 20 -name clkin_50 [get_ports {clkin_50}]# create_clock -period 8 -name clkin_125 [get_ports {clkin_125}]
create_clock -period 100 -name tck [get_ports {altera_reserved_tck}]
create_clock -period 8 -name virtual_enet_rx_clk_125M
create_clock -period 40 -name virtual_enet_rx_clk_25M
create_clock -period 400 -name virtual_enet_rx_clk_2M5
create_clock -period 8 -name enet_rx_clk_125M [get_ports {enet_rx_clk}]
create_clock -period 40 -name enet_rx_clk_25M [get_ports {enet_rx_clk}] -add
create_clock -period 400 -name enet_rx_clk_2M5 [get_ports {enet_rx_clk}] -add
create_clock -period 40 -name enet_tx_clk_25M [get_ports {enet_tx_clk}]
create_clock -period 400 -name enet_tx_clk_2M5 [get_ports {enet_tx_clk}] -add# **************************************************************# Create Generated Clock# **************************************************************
create_generated_clock -name enet_gtx_clk -source [get_pins {this_stratixIII_3sl150_dev_niosII_standard_sopc|the_sys_pll|the_pll|altpll_component|auto_generated|pll1|clk[1]}] [get_ports {enet_gtx_clk}]# **************************************************************# Set Clock Latency# **************************************************************
# **************************************************************# Set Clock Uncertainty# **************************************************************
# **************************************************************# Set Input Delay# **************************************************************
set_input_delay -clock { virtual_enet_rx_clk_125M } -min 0 [get_ports {enet_rx_col enet_rx_crs enet_rx_d[0] enet_rx_d[1] enet_rx_d[2] enet_rx_d[3] enet_rx_d[4] enet_rx_d[5] enet_rx_d[6] enet_rx_d[7] enet_rx_dv enet_rx_er}]
set_input_delay -clock { virtual_enet_rx_clk_125M } -max -add_delay 6 [get_ports {enet_rx_col enet_rx_crs enet_rx_d[0] enet_rx_d[1] enet_rx_d[2] enet_rx_d[3] enet_rx_d[4] enet_rx_d[5] enet_rx_d[6] enet_rx_d[7] enet_rx_dv enet_rx_er}]
set_input_delay -clock { virtual_enet_rx_clk_25M } -min -add_delay 9.5 [get_ports {enet_rx_col enet_rx_crs enet_rx_d[0] enet_rx_d[1] enet_rx_d[2] enet_rx_d[3] enet_rx_d[4] enet_rx_d[5] enet_rx_d[6] enet_rx_d[7] enet_rx_dv enet_rx_er}]
set_input_delay -clock { virtual_enet_rx_clk_25M } -max -add_delay 30.5 [get_ports {enet_rx_col enet_rx_crs enet_rx_d[0] enet_rx_d[1] enet_rx_d[2] enet_rx_d[3] enet_rx_d[4] enet_rx_d[5] enet_rx_d[6] enet_rx_d[7] enet_rx_dv enet_rx_er}]
set_input_delay -clock { virtual_enet_rx_clk_2M5 } -min -add_delay 9.5 [get_ports {enet_rx_col enet_rx_crs enet_rx_d[0] enet_rx_d[1] enet_rx_d[2] enet_rx_d[3] enet_rx_d[4] enet_rx_d[5] enet_rx_d[6] enet_rx_d[7] enet_rx_dv enet_rx_er}]
set_input_delay -clock { virtual_enet_rx_clk_2M5 } -max -add_delay 390.5 [get_ports {enet_rx_col enet_rx_crs enet_rx_d[0] enet_rx_d[1] enet_rx_d[2] enet_rx_d[3] enet_rx_d[4] enet_rx_d[5] enet_rx_d[6] enet_rx_d[7] enet_rx_dv enet_rx_er}]

# **************************************************************# Set Output Delay# **************************************************************
set_output_delay -clock { enet_gtx_clk } -min -0.5 [get_ports {enet_tx_d[0] enet_tx_d[1] enet_tx_d[2] enet_tx_d[3] enet_tx_d[4] enet_tx_d[5] enet_tx_d[6] enet_tx_d[7] enet_tx_en enet_tx_er}]
set_output_delay -clock { enet_gtx_clk } -max -add_delay 2.5 [get_ports {enet_tx_d[0] enet_tx_d[1] enet_tx_d[2] enet_tx_d[3] enet_tx_d[4] enet_tx_d[5] enet_tx_d[6] enet_tx_d[7] enet_tx_en enet_tx_er}]
set_output_delay -clock { enet_tx_clk_25M } -min -add_delay -1.5 [get_ports {enet_tx_d[0] enet_tx_d[1] enet_tx_d[2] enet_tx_d[3] enet_tx_d[4] enet_tx_d[5] enet_tx_d[6] enet_tx_d[7] enet_tx_en enet_tx_er}]
set_output_delay -clock { enet_tx_clk_25M } -max -add_delay 9.5 [get_ports {enet_tx_d[0] enet_tx_d[1] enet_tx_d[2] enet_tx_d[3] enet_tx_d[4] enet_tx_d[5] enet_tx_d[6] enet_tx_d[7] enet_tx_en enet_tx_er}]
set_output_delay -clock { enet_tx_clk_2M5 } -min -add_delay -1.5 [get_ports {enet_tx_d[0] enet_tx_d[1] enet_tx_d[2] enet_tx_d[3] enet_tx_d[4] enet_tx_d[5] enet_tx_d[6] enet_tx_d[7] enet_tx_en enet_tx_er}]
set_output_delay -clock { enet_tx_clk_2M5 } -max -add_delay 9.5 [get_ports {enet_tx_d[0] enet_tx_d[1] enet_tx_d[2] enet_tx_d[3] enet_tx_d[4] enet_tx_d[5] enet_tx_d[6] enet_tx_d[7] enet_tx_en enet_tx_er}]
# **************************************************************# Set Clock Groups# **************************************************************
set_clock_groups -exclusive -group this_stratixIII_3sl150_dev_niosII_standard_sopc|the_altmemddr|altmemddr_controller_phy_inst|alt_mem_phy_inst|altmemddr_phy_alt_mem_phy_siii_inst|clk|half_rate.pll|altpll_component|auto_generated|pll1|clk[0]
set_clock_groups -exclusive -group this_stratixIII_3sl150_dev_niosII_standard_sopc|the_sys_pll|the_pll|altpll_component|auto_generated|pll1|clk[0]
set_clock_groups -exclusive -group clkin_50# set_clock_groups -exclusive -group clkin_125# set_clock_groups -exclusive -group tck
set_clock_groups -exclusive -group [get_clocks {virtual_enet_rx_clk_125M enet_rx_clk_125M enet_gtx_clk}] -group [get_clocks {virtual_enet_rx_clk_25M enet_rx_clk_25M enet_tx_clk_25M}] -group [get_clocks {virtual_enet_rx_clk_2M5 enet_rx_clk_2M5 enet_tx_clk_2M5}]
# **************************************************************# Set False Path# **************************************************************
set_false_path -from [get_clocks {this_stratixIII_3sl150_dev_niosII_standard_sopc|the_sys_pll|the_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {enet_tx_clk_2M5}]
set_false_path -from [get_clocks {enet_tx_clk_2M5}] -to [get_clocks {this_stratixIII_3sl150_dev_niosII_standard_sopc|the_sys_pll|the_pll|altpll_component|auto_generated|pll1|clk[1]}]
set_false_path -from [get_clocks {this_stratixIII_3sl150_dev_niosII_standard_sopc|the_sys_pll|the_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {enet_tx_clk_25M}]
set_false_path -from [get_clocks {enet_tx_clk_25M}] -to [get_clocks {this_stratixIII_3sl150_dev_niosII_standard_sopc|the_sys_pll|the_pll|altpll_component|auto_generated|pll1|clk[1]}]
set_false_path -from [get_clocks {virtual_enet_rx_clk_125M virtual_enet_rx_clk_25M virtual_enet_rx_clk_2M5}] -to [get_clocks {this_stratixIII_3sl150_dev_niosII_standard_sopc|the_sys_pll|the_pll|altpll_component|auto_generated|pll1|clk[1]}]
set_false_path -from [get_clocks {this_stratixIII_3sl150_dev_niosII_standard_sopc|the_sys_pll|the_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {enet_rx_clk_2M5 enet_rx_clk_25M enet_rx_clk_125M}]
set_false_path -from [get_clocks {virtual_enet_rx_clk_25M}] -to [get_clocks {enet_tx_clk_25M}]
set_false_path -from [get_clocks {virtual_enet_rx_clk_2M5}] -to [get_clocks {enet_tx_clk_2M5}]
Altera_Forum
Honored Contributor
17 years ago
Hi Leon, thanks for all.
So if i understanded well, with the code you provided i have no to manually reset the Phy (actually i connect the enet_resetn to a user button to reset Phy). Do you think this code is good for all boards that have Marvell phy?

Bye
Altera_Forum
Honored Contributor
16 years ago
leonchang0000 (http://www.alteraforum.com/forum/member.php?u=6116), could you please specify the location to insert your patch in "altera_avalon_tse.c" file. Please, write strings after which I should insert your text.
If I am trying to use TSE in RGMII, do I need your patch, or it is useless?

Thanks.
Altera_Forum
Honored Contributor
16 years ago
I understood about RGMII.. I have to change the code a little to use.
Altera_Forum
Honored Contributor
16 years ago
Yup.. I guess so..
Altera_Forum
Honored Contributor
16 years ago
Hey.. man, please read the thread carefully.. I already specified the line number to insert..
Altera_Forum
Honored Contributor
16 years ago
Good day, leonchang0000 (http://www.alteraforum.com/forum/member.php?u=6116). I have read the thread carefully and noticed about the line 1233, but my file is modified or it's just a newer version, so the line 1233 is just between
alt_32 alt_tse_mac_group_init() and
alt_32 alt_tse_mac_get_phy() routines. I guess the code should be inserted into alt_32 alt_tse_mac_get_phy()?
Altera_Forum
Honored Contributor
16 years ago
Oki.. I see. no problems.. Herer i attach the source code here and please compare yourself.. it's pretty much based on 8.0.
altera_avalon_tse.txt93 KB
Altera_Forum
Honored Contributor
16 years ago
Thanks a lot))

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Triple speed ethernet and Marvell Phy on Stratix III

29 Replies

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