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Armando1989's avatar
Armando1989
Icon for Occasional Contributor rankOccasional Contributor
1 year ago
Solved

TRI STATE BUS

Hi guys I was doing some altera max7128 cpld vs 32k sram r/w interfacing. Basically write received rs232 words to ram till memory is fill, then read it back and transfer to rs232. What i want to kn...
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  • FvM's avatar
    FvM
    1 year ago

    Hi,

    basically it's the correct way to implement a bidirectional data bus, e.g. for external SRAM.

    The necessity of a busy state holding write data is questionable at first sight, but timing should be verified against SRAM specification or preferably a SRAM simulation model.

    Regards

    Frank

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,

basically it's the correct way to implement a bidirectional data bus, e.g. for external SRAM.

The necessity of a busy state holding write data is questionable at first sight, but timing should be verified against SRAM specification or preferably a SRAM simulation model.

Regards

Frank