Occasional ContributorTRI STATE BUS
Hi guys
I was doing some altera max7128 cpld vs 32k sram r/w interfacing. Basically write received rs232 words to ram till memory is fill, then read it back and transfer to rs232.
What i want to know is if "inout tri" is ok to sinthesize tristate bus?... below is system top module and the submodules that deal with the bus itself, ive added on all the same type of "inout tri" data, however im not sure if it was just required on "sram_R_W":
Also, in sram_R_W module, i stated to either write whats present on DATA receibed from rs232 or float the bus if not on write operation, so i suppose quartus understand the bus driver has to be tristate just by having applied "z" on it right?
and apparently, based on simulation it confirms bus floats when not writen:
Based on technology post fit, it indeed created a bidirectional port:
Attached for ur reference project with testbench and simulation.
May u confirm my thoughts? just dont want have bus contention issues, any suggestion is welcome!
Thanks in advance!
Hi,
basically it's the correct way to implement a bidirectional data bus, e.g. for external SRAM.
The necessity of a busy state holding write data is questionable at first sight, but timing should be verified against SRAM specification or preferably a SRAM simulation model.Regards
Frank
