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Altera_Forum
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16 years ago

TRDB-D5M with Cyclone 3 Development board

Hello My name is Hardik Shah,

I am using Terasic camera(with HSMC->40 pin converter) with Cyclone 3 board and trying to display the images taken by the camera on the HSMC Multimedia display.

- I use the camera in the free running mode which is by default.

- I do not use the I2C interface to communicate with the camera as we do not intend to use any NIOS processors.

- Row and Column skipping are implemented in the hardware to reduce the resolution.

- I am getting the waveforms as shown in the attached screen shot.

- I have tested the LCD interface by creating the on FPGA model of the camera. Which generates various colour bands in bayer pattern and inputs them to the camera interface.

From the camera interface till the LCD, everything works according to the specification. But, when I connect the real camera with board, the LCD displays only noisy colours.

Are there any know issues with the camera?

Can you suggest me what I may take into consideration?

Kindly, reply as soon as possible.

Best regards,

Hardik Shah

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  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi BVP,

    You are right an input clock should go to the EXTCLK pin of the camera and output clock from the camera PIXCLK should be feed in to the circuit that captures the frames. Both the clocks will have the same frequency (may be a slight phase shift). If you input 27 MHz clock to the camera, you will receive 27M pixels per second. The camera output is in the bayer pattern, you need to convert it into the RGB. Afterwards calculate number of pixels you have per frame to come up with frame rate.

    HTH,

    Hardik
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi Hardik,

    Thanks for your quick response. I got it clear now.

    When you say to calculate the no. of pixels, do you mean to configure the Sensor Row and Column Size registers (0x03 and 0x04)?

    I now have a row size set as 2047 and column as 2559. I also use row and column skipping to skip every alternate row and column and also binning set as 1 ( Registers 0x023 and 0x024). Now from one the tables in the TRDB-D5M datasheet, I understand that such a configuration would result in a resolution of 1280x1024 and a Frame rate of 40.1

    Is my understanding right on deriving my Frame Rate? :confused:

    Kindly comment.

    Best Regards,

    BVP
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi BVP,

    I am sorry I cannot help you in this. The reason is I did this project about 2 years ago and I do not remmember the details you have asked for.

    I will have to re-read the manual :(

    Regards.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi,

    Just thought to share ... I was reading through the hardware specification and found out that the PIXCLK frequency can be altered by configuring the PLL register in the camera.

    In my case PLL Config1 and Config2 (Output frequency multiplier) are configured as:

    PLL_n_Divide = 4, PLL_m_Factor = 24 and PLL_p1_Divide = 1

    Then, pixclk = (xclkin x m)/(n x p1) where, M is the PLL_m_Factor, N is the PLL_n_Divider+1 and P1 is PLL_p1_Divider+1

    25Mhz clock is fed into the XCLKIN TRDB pin and by using the above equation PIXCLK (output rate of camera) is 60Mhz/60Mpps. Confirmed this on the scope!
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    hi BVP and HARDIK,

    do you mind sharing your code? the former posts says it's in vhdl. i have DE2 and the 5Megapixel camera module but i dont know verilog. I was hoping to see your code and have a look on how it's done.

    thanks.

    hoping,

    glenn