TRDB-D5M with Cyclone 3 Development board

Hi,

Just thought to share ... I was reading through the hardware specification and found out that the PIXCLK frequency can be altered by configuring the PLL register in the camera.

In my case PLL Config1 and Config2 (Output frequency multiplier) are configured as:

PLL_n_Divide = 4, PLL_m_Factor = 24 and PLL_p1_Divide = 1

Then, pixclk = (xclkin x m)/(n x p1) where, M is the PLL_m_Factor, N is the PLL_n_Divider+1 and P1 is PLL_p1_Divider+1

25Mhz clock is fed into the XCLKIN TRDB pin and by using the above equation PIXCLK (output rate of camera) is 60Mhz/60Mpps. Confirmed this on the scope!