Forum Discussion
MuhammadAr_U_Intel
Contributor
6 years agoHi,
To answer your first question where few stages doesn't appear, this might be due to rest of the stages were getting optimized since output is not used, you might want to look for why are they optimized.
Secondly what is the target frequency you have selected to constrain the design, you should look for static timing analysis report to find if the design can run on desired frequency, in case it failed in reports you can reduce frequency or try to optimize the design.
Hope this helps.
Thanks,
Arslan