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Altera_Forum's avatar
Altera_Forum
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15 years ago

transceiver design examples

Hi, I would like to modify a design example named aii_4ch_10b_2000Mbps (transceiver design example) in order to use CMU PLL0 for first two channels and CMU PLL1 for the other two. I have a c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I enabled the Custom PHY Transceiver doing as you suggested.

I didn't expect that a tool like Quartus could have such problems.

Furthemore, with Qsys I cannot select CMU PLL0/1 for a given channel and it is not clear which relation there should be between input reference clock and Data Rate.