TNT Consultation Request ID [3212] - Sequential Routing for Memory AGILEX

Hi Chris,

The Shallow Row and Deep Row are assigned to the adjacent bytes in the row.

From my understanding, the pins are grouping in 5 row to group as byte or bytes in column.

For example, the row DR,DP,DM,DN,DL will have at least one byte and the row DK,DJ,DH,DG,DF will have another adjacent bytes.

To alternate adjacent FPGA EMIF ball rows with deep and shallow board via transitions, the row DR,DP,DM,DN,DL will be Shallow Row and DK,DJ,DH,DG,DF will be Deep Row.

Same goes to the other rows for adjacent bytes.

The pin function can be checked in the Pin-Out file for the targeted device.

Regards,

Adzim