Timing violation when route emac from HPS to FPGA in quartus prime standard 18.1

Hi Lijiao,

I almost forgot, those are ddio path. Only ddio path are entitied to have generated_clock to data in the timing analyzer.

With that said, you have the correct constrain. However, your design are failling at setup and hold at the same time. There are no way to close timing having it fail at the same time, this means that base on your requirement, it cannot run so fast on that pin. You may have to tune the output_delay value or reduce the frequency if necessary.

If you failed only on one of the edges, you can tune the D1 to D5 delay on the pin. That is also you have to see whether pin IO standard can run so fast or not.

Since the original design is created by rocket board, they have not close the timing as you mention the design originally run on Q14.0 and Q14.1 and the timing not close.