Occasional Contributor
Super ContributorThis cv_soc_rgmii_5csxfc6:soc_0|cv_soc_rgmii_5csxfc6_hps_0:hps_0|cv_soc_rgmii_5csxfc6_hps_0_fpga_interfaces:fpga_interfaces|peripheral_emac0~internal_clock
should not be a data path. it is a clock path. If it is not a clock, you will not set this in your sdc files:
### RGMII TX clock 125/25/2.5MHz ###
create_clock -name TX_SRC_CLK_125 -period "125 MHz" [get_keepers {soc_0|hps_0|fpga_interfaces|peripheral_emac0~internal_clock}] -add
create_clock -name TX_SRC_CLK_25 -period "25 MHz" [get_keepers {soc_0|hps_0|fpga_interfaces|peripheral_emac0~internal_clock}] -add
create_clock -name TX_SRC_CLK_2_5 -period "2.5 MHz" [get_keepers {soc_0|hps_0|fpga_interfaces|peripheral_emac0~internal_clock}] -add
Theoretically, we analyze from node to to node with a data path, the launch and latch is for the clock path. I would suggest you false path this. Thanks
Occasional ContributorHi,
Thank you very much for the reply.
I set false paths to all the paths from cv_soc_rgmii_5csxfc6:soc_0|cv_soc_rgmii_5csxfc6_hps_0:hps_0|cv_soc_rgmii_5csxfc6_hps_0_fpga_interfaces:fpga_interfaces|peripheral_emac0~internal_clock
to phy_rgmii_rgmii_txd[*]
Then I notice there is no path analyzed from TX_SRC_CLK_125 to TX_OUT_CLK_125.
Then what is the point to set output delay like this:
set_output_delay -clock TX_CLK_OUT_125 -max $output_max_delay [get_ports "phy_rgmii_rgmii_txd* phy_rgmii_rgmii_tx_ctl"]
Because the output delay is set and supposed to be analyzed from TX_SRC_CLK_125 to TX_OUT_CLK_125 (according to AN433 and AN477).
I attached the new design here after I set the false paths.
