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Mingyuexin's avatar
Mingyuexin
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Timing violation when route emac from HPS to FPGA in quartus prime standard 18.1

Hi, I need to use route EMAC from HPS to FPGA because our system need 4 channels of ethernets, and one USB interface also. I refer to the examples from here https://rocketboards.org/foswiki/Projec...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
6 years ago
Looking into the timing violation cv_soc_rgmii_5csxfc6:soc_0|cv_soc_rgmii_5csxfc6_hps_0:hps_0|cv_soc_rgmii_5csxfc6_hps_0_fpga_interfaces:fpga_interfaces|peripheral_emac0~internal_clock phy_rgmii_rgmii_txd[1] TX_SRC_CLK_125 TX_CLK_OUT_125 Will there be a data transfer from this internal_clock to the phy? If no, you can false path it.