Timing violation when route emac from HPS to FPGA in quartus prime standard 18.1

Looking into the timing violation cv_soc_rgmii_5csxfc6:soc_0|cv_soc_rgmii_5csxfc6_hps_0:hps_0|cv_soc_rgmii_5csxfc6_hps_0_fpga_interfaces:fpga_interfaces|peripheral_emac0~internal_clock phy_rgmii_rgmii_txd[1] TX_SRC_CLK_125 TX_CLK_OUT_125 Will there be a data transfer from this internal_clock to the phy? If no, you can false path it.