Timing violation when route emac from HPS to FPGA in quartus prime standard 18.1

Thanks for your attachment, I review your sdc files,

#create_generated_clock -name TX_CLK_OUT_2_5 \

#-source [get_pins {ddio_out_1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0]|muxsel}] \

#-master_clock TX_SRC_CLK_2_5 [get_ports phy_rgmii_rgmii_tx_clk] -add

I can't to see this output pin -source [get_pins {ddio_out_1|ALTDDIO_OUT_component|auto_generated|ddio_outa[0]|muxsel}] \ in the rtl viewer. This should be a mux, the pin i found is

-source [get_pins {soc_0|gmii_to_rgmii_adapter_0|u_altera_gmii_to_rgmii_adapter_core|u_mac_tx_clock_input_mux|outclk|combout}] \

I see there are tans of ignore constrain in your design, you need to fix all the timing warning to make sure that there are no warning messages. As currently, the timing report does not seems make sense to me, it is failing from clock to data with reference with cross clock. Usually, the from node should be a data instead of a clock.

You can reattached the design after you fix all the ignored warning. Thanks