timing in I/O pads

Hi YY, Based on you gave me the application note 307 on page 77, I added QSF command as following as: set_instance_assignment -name PLACE_REGION "X126 Y58 X148 Y71" -to five_adc1_data set_instance_assignment -name RESERVE_PLACE_REGION -to five_adc1_data​ set_instance_assignment -name CORE_ONLY_PLACE_REGION -to five_adc1_data​ set_instance_assignment -name REGION_NAME five_adc1_data -to five_adc1_data​ set_instance_assignment -name ROUTE_REGION "X126 Y58 X148 Y71" -to five_adc1_data The above commands partially working because some logic placed that region now which previous this region is empty (you can open chip editor to reference my X-Y location to figure out in device 10AX027H4F34I3SG), so I think your R&D instantiated Synopsys command something like "create_placement_blockage -type soft". Would you know what is command for "-type hard" which I want to force them to go to different region? If it is already "hard", it seems a BUG in that condition. The reason is that current LAB is far away with GPIO which located left above location that cause the timing violation, and your Altera parse prefers that location even I put above QSF command, but this placement causes my timing problem in my case. Please see the attachment for the arrow points for net connections. Again I can not give you testcase, but all necessary info I already explain for the R&D debug. It is urgent, and please ask your R&D puts some effort since my board will come back next week. This is the only problem that I can image now, so please help me:) Thank you so much in advance. [cid:a5d0808e-0e28-4c4a-b3c0-c0611c773be9] Thanks, -Fred