Hello, Currently, I passed all setup, hold, recovery and removal timing within the FPGA with constraint all paths and I/Os, but my I/O through GPIO portion did not passed the timing. Do you have any...
Hi YY,
Thank you so much for your information, and I will review it. From Chip editor, I saw the GPIO very close with its pin which it is in the same IOB block, so manually move the cell option is gone. I read your link about Xilinx with Altera comparison paper, and I found there is one option for the compiler setting for three options. Currently I put default, so I would like to try aggressive option. However, I meet memory issue again …
Thanks,
-Fred
Hi YY,
Based on you gave me the application note 307 on page 77, I added QSF command as following as:
set_instance_assignment -name PLACE_REGION "X126 Y58 X148 Y71" -to five_adc1_data
set_instance_assignment -name RESERVE_PLACE_REGION -to five_adc1_data
set_instance_assignment -name CORE_ONLY_PLACE_REGION -to five_adc1_data
set_instance_assignment -name REGION_NAME five_adc1_data -to five_adc1_data
set_instance_assignment -name ROUTE_REGION "X126 Y58 X148 Y71" -to five_adc1_data
The above commands partially working because some logic placed that region now which previous this region is empty (you can open chip editor to reference my X-Y location to figure out in device 10AX027H4F34I3SG), so I think your R&D instantiated Synopsys command something like "create_placement_blockage -type soft". Would you know what is command for "-type hard" which I want to force them to go to different region? If it is already "hard", it seems a BUG in that condition. The reason is that current LAB is far away with GPIO which located left above location that cause the timing violation, and your Altera parse prefers that location even I put above QSF command, but this placement causes my timing problem in my case. Please see the attachment for the arrow points for net connections. Again I can not give you testcase, but all necessary info I already explain for the R&D debug. It is urgent, and please ask your R&D puts some effort since my board will come back next week. This is the only problem that I can image now, so please help me:) Thank you so much in advance.
[cid:a5d0808e-0e28-4c4a-b3c0-c0611c773be9]
Thanks,
-Fred
Hi YY,
How to interpret FF_X149_Y78_N16 for number of 16? How about I have LAB_X149_Y72_N0 convert to FF_X149_Y72_N?? what is tool behavior?
Thanks,
-Fred
Don’t worry about this issue and I know how to interpret the LAB location now, but I don’t know why timing report didn’t change. As I know Synopsys timing report should change even some 10 pico second change. Could do some experiment in your side with any small testcase? I really feel wired for the timing report even I locked different location. Thank you in advance!
Oh the command is set_location_assignment is hard lock
I am sorry for the late reply. We have Public holiday after the weekend.
What kind of experiment you would like to do? May I know the changes you have made and the result that you think is not expected. Sure. You may provide the testcase and let me know the steps and expected result.
HI YY,
I see. Thanks for your quick response. Currently I add new commands in qsf file as following as:
set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataL[2]"
set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataL[0]"
set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataH[3]"
set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataL[1]"
set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataL[6]"
set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataH[6]"
set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataH[2]"
set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataH[0]"
set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataL[3]"
set_location_assignment LAB_X149_Y70_N0 -to "image_sampling:module_image_sampling|adc_sample_top:adc_sample_inst|adc100mhz_interface:adc_sample|sig5Adc0Bank1DataH[1]"
The timing report is still has [cid:cdf2b8ff-bd8b-41ee-9023-b788567e7ff3]
The floorplan placement which matches constrain as following as
[cid:74445102-84c9-44b8-a9af-dc4882e6e8be]
Before I put above constraints, the floorplan placement is as below routing with same report delay, but routing distance cross a lot of LABs comparing above and below placement, so I suspect timing report is wrong. As I did Synopsys ICC2 timing project back three years ago, these distances should have different timing report because net delay has a big difference. Since I/O pads fix the location, you can figure out rest of constrains to do experiments.
[cid:7fd1c7c8-fc24-4aac-9c3e-92c450438757]
I used 10AX027H4F34I3SG device.
Thank you so much!
-Fred
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